Planar transistors in the integrated circuit industry are usually manufactured onto a semiconductor substrate, such as silicon. The semiconductor substrate, even when doped, is usually more resistive than most metal-containing materials. Resistive contacts and interconnects are not desirable for electrical circuits due to the fact that resistance limits maximum current flow, may create heat, and may result in reduced circuit accuracy, consistency, and performance. Therefore, metal oxide semiconductor (MOS) transistors which have silicided or salicided source regions, drain regions, and gate regions are typically used.
One method for forming a silicided/salicided drain, source, and gate for a transistor starts by providing a substrate. A gate, usually made of polysilicon is formed overlying the substrate. Source and drain regions are ion implanted and self-aligned to the gate. A layer of refractory metal, such as titanium, tantalum, platinum, nickel, and cobalt, is sputtered or deposited over the exposed source, drain, and gate regions. A heating step ranging from 200.degree. C. to 650.degree. C., which depends upon the type of metal used, is performed to form a self-aligned silicide region on the gate, drain, and source simultaneously. The silicide on the gate, source, and drain are all formed as the same silicide (i.e. one of either CoSi.sub.2, TiSi.sub.2, TaSi.sub.2, or the like).
There are disadvantages to forming all of a transistor's electrodes (i.e. gate, source, and drain) with a single type of silicide region. For example, some silicides, such as platinum silicide, are not stable at high temperatures and will be damaged during subsequent high temperature processing. Furthermore, one silicide region is usually not advantageous for use with both current electrodes (i.e. source and drain) and gate electrodes. For example, cobalt silicide laterally diffuse dopants quickly at high temperatures (greater than 600.degree. C.). This lateral diffusion may counter-dope or alter doping concentrations in gate regions and/or buried contact connection regions. Also, cobalt silicide is less thermally stable on polysilicon than on single crystalline silicon. Cobalt silicides degrade by agglomeration between 850.degree. C. and 900.degree. C. on polysilicon, whereas cobalt silicides are stable to 1000.degree. C. on single crystalline silicon. Therefore, cobalt silicide is not an optimal gate electrode silicide. Titanium silicide has segregation coefficients with dopants such as boron, arsenic, and phosphorus, which results in under-doped or damaged source and drain contact regions, and unwanted titanium boride and/or titanium arsenide compounds formed at the silicide-silicon interface. Therefore, titanium silicide is not optimal for use with source and drain electrodes.
To overcome some of these disadvantages, transistors were formed by another method. This alternative method involved forming one silicide overlying the gate region, and another silicide overlying the source and drain regions. The method starts by providing a silicon substrate. A gate oxide, gate electrode (i.e. polysilicon), and refractory metal stack is formed over the substrate. The gate oxide, gate electrode (i.e. polysilicon), and refractory metal stack is etched, starting with the top refractory metal layer, to define gate electrodes. A heat cycle then reacts the refractory metal layer with the gate electrode to form a first silicide region self-aligned to the gate. A second refractory deposition or sputtering step is used to form a second refractory metal layer over the source and drain regions. A second heat cycle is used to form a second silicide region over the source and drain regions.
This method of forming a first silicided region and a second silicided region for an MOS transistor has some disadvantages. One disadvantage is that the etch processing required to etch a refractory metal over polysilicon is complicated and requires multiple etch steps. The etch steps may result in undercutting of the polysilicon gate and adverse alteration of transistor channel dimensions. The chemistries required for the etching of refractory metals and polysilicon do not result in adequate selectivity in some cases. Therefore, the etch steps used to remove the refractory metal and polysilicon may not consistently end point on a thin (i.e. 40-150 Angstrom) gate oxide, and may result in pitting of the substrate. The etch step described above will leave composite polysilicon/metal stringers (i.e. unwanted spacers) which are well documented in the art. These stringers are usually removed via an isotropic etch or an overetch process. These chemistries, when removing composite stringers are complex and not always successful. In some cases, an aggressive stringer removal process will also attack/damage the silicide regions.
Therefore, the need exists for an improved process which may be used to form a first silicide region for gate electrodes and a second silicide region for source and drain electrodes.